One design flow for creating a circuit design and implementing a circuit involves entering the initial design via a block diagramming environment such as the SIMULINK® environment. After the initial circuit design is specified as a block diagram, functionally equivalent high-level programming language (HLL) code (e.g., C++ code) can be generated. The C++ code can then be synthesized into a hardware specification, such as a configuration bitstream targeted to a field programmable gate array (FPGA) using a high-level synthesis (HLS) tool.
The generated HLL code generally consists of a function that computes a sample of the output ports of the block diagram as a function of the samples of the input ports of the block diagram. The function may be composed from HLL code fragments that implement each of the blocks of the block diagram. For some applications, such as image and video processing, directives are included in the HLL code to promote a streaming and pipelined architecture. Thus, each block from the original block diagram can be translated into an individual task of a pipelined circuit.
The generated HLL code may fail to deliver a quality-of-result (QoR) in the resulting circuit comparable to the QoR achievable from hand-written HLL code. The QoR can be quantified using factors such as the maximum clock frequency, at which the resulting circuit can operate correctly, the resource utilization of circuitry on a target device (e.g., an FPGA), latency of a circuit, and/or throughput of a circuit. When tasks as represented by code fragments in the HLL code correspond to blocks in the block diagram, the HLS optimizes each task individually. If the complexity of each task is low, the QoR may be inferior to the QoR that can be achieved from fewer, more complex, tasks that a designer might have hand coded.